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IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
IDT74FCT88915TT 55/70/100/133
FEATURES:
DESCRIPTION:
* 0.5 MICRON CMOS Technology * Input frequency range: 10MHz - f2Q Max. spec (FREQ_SEL = HIGH) * Max. output frequency: 133MHz * Pin and function compatible with MC88915 * Five non-inverting outputs, one inverting output, one 2x output, one /2 output; all outputs are TTL-compatible * Output Skew < 500ps (max.) * Duty cycle distortion < 500ps (max.) * Part-to-part skew: 0.55ns (from tPD max. spec) * 64/-15mA drive at TTL output voltage levels * Available in PLCC and SSOP packages
The FCT88915TT uses phase-lock loop technology to lock the frequency and phase of outputs to the input reference clock. It provides low skew clock distribution for high performance PCs and workstations. One of the outputs is fed back to the PLL at the FEEDBACK input resulting in essentially zero delay across the device. The PLL consists of the phase/frequency detector, charge pump, loop filter and VCO. The VCO is designed to run optimally between 20MHz and f2Q Max. The FCT88915TT provides eight outputs with 500ps skew. The Q5 output is inverted from the Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs at half the Q frequency. The FREQ_SEL control provides an additional / 2 option in the output path. PLL _EN allows bypassing of the PLL, which is useful in static test modes. When PLL_EN is low, SYNC input may be used as a test clock. In this test mode, the input frequency is not limited to the specified range and the polarity of outputs is complementary to that in normal operation (PLL_EN = 1). The LOCK output attains logic high when the PLL is in steady-state phase and frequency lock. The FCT88915TT requires external loop filter components as recommended in Figure 2.
FUNCTIONAL BLOCK DIAGRAM
FEEDBAC K Voltage Controlled Oscilator LF REF_SEL PLL_EN 0 1 Mux (/ 1) Divide -By-2 FREQ_SEL RST 1M u 0x
D CP D CP R D CP R D CP D CP D CP D CP R
R R R
LOCK
SYNC (0) SYNC (1)
0M u 1x
Phase/Freq. Detector
C harge Pump
2Q
Q
RQ
Q0
(/ 2)
Q
Q1
Q
Q2
Q
Q3
Q
Q4
Q
Q5
Q
Q/2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
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(c) 2001 Integrated Device Technology, Inc.
MARCH 2001
DSC-4245/2
IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
GND RST VCC VCC Q4 2Q Q5
4 FEEDBK REF_SEL SYNC(0) VCC(AN) LF GND(AN) SYNC(1) 5 6 7 8 9 10 11 12
FREQ_SEL
3
2
1
28
27
26 25 24 23 22 21 20 19 Q/2 GND Q3 VCC Q2 GND LOCK
GND Q5 VCC RST FEEDBACK REF_SEL SYNC(0) VCC(AN) LF GND(AN) SYNC(1) FREQ_SEL GND Q0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Q4 VCC 2Q Q/2 GND Q3 VCC Q2 GND LOCK PLL_EN GND Q1 VCC
13
GND
14
Q0
15
VCC
16
Q1
17
GND
18
PLL_EN
PLCC TOP VIEW
SSOP TOP VIEW
PIN DESCRIPTION
Pin Name SYNC(0) SYNC(1) REF_SEL FREQ_SEL FEEDBACK LF Q0-Q4 Q5 2Q Q/2 LOCK RST PLL_EN I/O I I I I I I O O O O O I I Description Reference clock input Reference clock input Chooses reference between SYNC (0) & SYNC (1) (refer to functional block diagram) Selects between / 1 and / 2 frequency options (refer to functional block diagram) Feedback input to phase detector Input for external loop filter connection Clock outputs Inverted clock output Clock output (2 x Q frequency) Clock output (Q frequency / 2) Indicates phase lock has been achieved (HIGH when locked) Asynchronous reset (active LOW) Disables phase-lock for low frequency testing (refer to functional block diagram)
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IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) TA TBIAS TSTG IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias StorageTemperature DC Output Current Max. -0.5 to 7 -0.5 to VCC+0.5 0 to +70 -55 to +125 -55 to +125 -60 to 120 Unit V V C C C mA
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 4.5 5.5 Max. 6 8 Unit pF pF
NOTE: 1. This parameter is measured at characterization but not tested.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals. 3. Outputs and I/O terminals.
SYNC INPUT TIMING REQUIREMENTS
Symbol TRISE/FALL Frequency Duty Cycle Parameter Rise/Fall Times, SYNC inputs (0.8V to 2.0V) Input Frequency, SYNC Inputs Input Duty Cycle, SYNC Inputs Min. -- 10 25% Max. 3 2Q fmax 75% Unit ns MHz --
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to 70C, VCC = 5.0V 5%
Symbol VIH VIL IIH IIL VIK VIH VOH VOL ICCL ICCH Parameter Input HIGH Level Input LOW Level Input HIGH Current Input LOW Current Clamp Diode Voltage Input Hysteresis Output HIGH Voltage Output LOW Voltage Quiescent Power Supply Current VCC = Min. VCC = Min. VCC = Max., VIN = GND or VCC (Test mode, LF connected to GND) VCC = Min., IIN = -18mA -- IOH = -15mA IOL = 64mA Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max. VI = VCC VI = GND Min. 2 -- -- -- -- -- 2.4 -- -- Typ.(2) -- -- -- -- -0.7 100 3.5 0.2 2 Max. -- 0.8 1 1 -1.2 -- -- 0.55 4 Unit V V A A V mV V V mA
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
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IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD CPD IC Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Power Dissipation Capacitance Total Power Supply Current(5,6) Test Conditions(1) VCC = Max. VIN = VCC -2.1V(3) VCC = Max. VIN = VCC All Outputs Open VIN = GND 50% Duty Cycle VCC = Max. PLL_EN = 1, LOCK = 1, FEEDBACK = Q4 SYNC frequency = 50MHz. Q4 loaded with 50pF. All other outputs open. VCC = Max. PLL_EN = 1, LOCK = 1, FEEDBACK = Q4 SYNC frequency = 50MHz. Q4 loaded with 50 Thevenin termination. All other outputs open. 50 Thevenin termination @ 33MHz 50 Paralell termination to GND @ 33MHz Min. -- -- -- -- Typ.(2) 0.5 0.5 25 65 Max. 1.5 0.7 40 80 Unit mA mA/ MHz pF mA
--
--
--
mA
PD1 PD2
Power Dissipation Power Dissipation
-- --
120 300
-- --
mW mW
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. It is derived with Q frequency as the reference. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (f) + ILOAD ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) f = 2Q frequency ILOAD = Dynamic Current due to load.
OUTPUT FREQUENCY SPECIFICATIONS
Max.(2) Symbol f2Q fQ fQ/2 Parameter Operating frequency 2Q Output Operating frequency Q0-Q4, Q5 Outputs Operating frequency Q/2 Output Min. 40 20 10 55 55 27.5 13.75 70 70 35 17.5 100 100 50 25 133 133 66.7 33.3 Unit MHz MHz MHz
NOTES: 1. Note 8 in "General AC Specification Notes" and Figure 2 describes this specification and its actual limits depending on the feedback connection. 2. Maximum operating frequency is guaranteed with the part in a phase locked condition and all outputs loaded with 50pF.
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IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tRISE/FALL All Outputs tRISE/FALL 2Q Output(3) tPULSE WIDTH Q, Q, Q/2 Outputs(3) tPULSE WIDTH 2Q Output(3) tPULSE WIDTH 2Q Output(3) tPD SYNC-FEEDBACK(3) tSKEWr (rising)(3, 4) tSKEWf (falling)(3, 4) tSKEWALL(3, 4) tLOCK(6) tRST Reset - Q tREC(10) tW(10) Parameter Rise/Fall Time (between 0.2 VCC and 0.8 VCC ) Rise/Fall Time (between 0.8V and 2.0V) Output Pulse Width Q0-Q4, Q5, Q/2 @ VCC/2 Output Pulse Width 2Q Output @ VCC/2 Output Pulse Width 2Q @ 1.5V SYNC input to FEEDBACK delay (measured at SYNC0 or 1 and FEEDBACK input pins) Output to Output Skew between outputs 2Q, Q0-Q4,Q/2 (rising edges only) Output to Output Skew between outputs 2Q, Q0-Q4 (falling edges only) Output to Output Skew 2Q, Q/2, Q0-Q4 rising, Q5 falling Time required to acquire Phase-Lock from time SYNC input signal is received Propagation Delay, RST (HIGH-to-LOW) to any Output (HIGH-to-LOW) Reset Recovery Time Rising RST edge to falling SYNC edge Minimum Pulse Width RST input LOW 5 -- ns
GENERAL AC SPECIFICATION NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested. 3. These specifications are guaranteed but not production tested. 4. Under equally loaded conditions, CL = 50pF (2pF), and at a fixed temperature and voltage. 5. tCYCLE = 1/frequency at which each output (Q, Q, Q/2 or 2Q) is expected to run. 6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1F, tLOCK Min. is with C1 = 0.01F (where C1 is loop filter capacitor shown in Figure 2). 7. These two specs ( tRISE/FALL and tPULSE WIDTH 2Q output) guarantee that the FCT88915TT meets 68040 P-Clock input specification. For these two specs to be guaranteed by IDT, the termination scheme shown in Figure 1 must be used:
Condition(1) CL = 50pF RL = 500 CL = 20pF & termination(7) CL = 50pF CL = 50pF Termination as in note 7 Load = 50 to VCC/2, CL = 20pF 0.1MF from LF to Analog GND(9) CL = 50pF
Min. 1(2) 0.5(2) 0.5tCYCLE - 0.5(5) 0.5tCYCLE - 1(5) 0.5tCYCLE - 0.5(5) -0.5
Max. 2.5 1.6 0.5tCYCLE + 0.5(5) 0.5tCYCLE + 1(5) 0.5tCYCLE + 0.5(5) +0.5
Unit ns ns ns ns ns ns
-- -- -- 1(2) 1.5(2) 9
500 500 500 10 8 --
ps ps ps ms ns ns
Rs 88915TT 2Q Output
Zo (clock trace)
68040 P-Clock Input
Rs = Zo - 7 Rp Rp = 1.5 Zo
Figure 1. MC68040 P-Clock Input Termination Scheme 5
IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
GENERAL AC SPECIFICATION NOTES, CONTINUED 8. The wiring diagrams and written explanations of Figures 4a-4c demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW. Also, it is possible to feed back the Q5 output, thus creating a 180 phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC frequency range for each possible configuration:
FREQ_SEL Level HIGH HIGH HIGH HIGH LOW LOW LOW LOW
Feedback Output Q/2 Any Q (Q0-Q4) Q5 2Q Q/2 Any Q (Q0-Q4) Q5 2Q
Allowable SYNC Input Frequency Range (MHz) 10 to (2Q fMAX Spec)/4 20 to (2Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2 40 to (2Q fMAX Spec) 5 to (2Q fMAX Spec)/8 10 to (2Q fMAX Spec)/4 10 to (2Q fMAX Spec)/4 20 to (2Q fMAX Spec)/2
Corresponding 2Q Output Frequency Range 40 to (2Q fMAX Spec) 40 to (2Q fMAX Spec) 40 to (2Q fMAX Spec) 40 to (2Q fMAX Spec) 20 to (2Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2 20 to (2Q fMAX Spec)/2
Phase Relationship of the Q Outputs to Rising SYNC Edge 0 0 180 0 0 0 180 0
9. The tPD spec describes how the phase offset between the SYNC input and the output connected to the FEEDBACK input varies with process, temperature, and voltage. The phase measurements were made at 1.5V. The Q/2 output was terminated at the FEEDBACK input with 100 to VCC and 100 to ground. tPD measurements were made with the loop filter connection shown in Figure 2 below:
LF External Loop Filter
0.1F
C1
Analog GND
Figure 2. Loop Filter Connection
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IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
BOARD VCC
COMMERCIAL TEMPERATURE RANGE
ANALOG VCC
10 F Low Freq. Bypass
0.1 F High Freq. Bypass
LF 0.1 F (Loop Filter Cap)
Analog loop filter/VCO section of the FCT88915TT
ANALOG G ND
BOARD GND
A separate Analog power supply is not necessary and should not be used. Following these prescribed guidelines is all that is necessary to use the FCT88915TT in a norm al digital environment.
Figure 3. Recommended Loop Filter and Analog Isloation Scheme for the FCT88915TT
NOTES: 1. Figure 3 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation: a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the LF pin. b. The 10F low frequency bypass capacitor and the 0.1F high frequency bypass capacitor form a wide bandwidth filter that will minimize the 88915TT's sensitivity to voltage transients from the system digital VCC supply and ground planes. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, VCC step deviations should not occur at the 88915TT's digital VCC supply. The purpose of the bypass filtering scheme shown in Figure 3 is to give the 88915TT additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. c. The loop filter capacitor (0.1F) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 2. In addition to the bypass capacitors used in the analog filter of Figure 3, there should be a 0.1F bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 88915TT outputs, in addition to reducing potential for noise in the "analog" section of the chip. These bypass capacitors should also be tied as close to the 88915TT package as possible.
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IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
25 MHz feedback signal 50 MHz signal
The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q/2 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q/2 and SYNC. Thus the Q/2 frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2 frequency.
HIGH RST FEEDBAC K LOW 25 MHz input REF_SEL SYNC(0) VCC(AN) LF FCT88915TT Q2 Q3 Q5 Q4 2Q Q/2 12.5 MHz signal 25 MHz "Q" Clock Outputs
50 MHz signal 12.5 M Hz feedback signal
GND(AN) FQ_SEL Q0 Q1 PLL_EN H IGH
HIG H
HIGH
RST Q5 Q4 2Q Q/2 FEED BACK LO W 12.5 M Hz input REF_SEL SYNC(0) VCC(AN) LF GND(AN) FQ_SEL Q0 HIGH Q1 PLL_EN HIGH FCT88915TT Q2 Q3 25 MHz "Q" Clock Outputs
Allowable Input Frequency Range: 20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL HIGH) 10MHz to (f2Q FMAX Spec)/4 (for FREQ_SEL LOW) Figure 4b. Wiring Diagram and Frequency Relationships with Q4 Output Feedback
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the 2Q output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of 2Q and SYNC. Thus the 2Q frequency will equal the SYNC frequency. The Q/2 output will always run at 1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
50 MH z feedback signal HIGH RST Q5 Q4 2Q Q/2 12.5 MHz input 25 MH z "Q" Clock Outputs
Allowable Input Frequency Range: 10MHz to (f2Q FMAX Spec)/4 (for FREQ_SEL HIGH) 5MHz to (f2Q FMAX Spec)/8 (for FREQ_SEL LOW) Figure 4a. Wiring Diagram and Frequency Relationships with Q/2 Output Feedback
LOW 50 MHz input
FEED BAC K REF_SEL SYN C(0) VCC(AN) FCT88915TT
Q3
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the Q4 output is connected to the FEEDBACK input. The internal PLL will line up the positive edges of Q4 and SYNC. Thus the Q4 frequency (and the rest of the "Q" outputs) will equal the SYNC frequency. The Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run at 2X the Q frequency.
LF GN D(AN) FQ_SEL Q0 Q1
Q2
PLL_EN HIGH
HIGH
Allowable Input Frequency Range: 40MHz to (f2Q FMAX Spec) (for FREQ_SEL HIGH) 20MHz to (f2Q FMAX Spec)/2 (for FREQ_SEL LOW) Figure 4c. Wiring Diagram and Frequency Relationships with 2Q Output Feedback 8
IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
CM M U FCT88915TT CLOCK @f PLL 2f CPU
CM M U
CPU CARD
CM M U
SYSTEM CLOCK SOURCE
CM M U
CM M U
CM M U FCT88915TT PLL 2f CPU
CM M U
CPU CARD
CM M U
DISTRIBUTE CLOCK @ f
CM M U
CM M U
CLOCK @ 2f at point of use
FCT88915TT PLL 2f ME MO RY CONTROL
ME MO RY CARDS CLOCK @ 2f at point of use
Figure 5. Multiprocessing Application Using the FCT88915 for Frequency Multiplication and Low Board-to-Board skew FCT88915 SYSTEM LEVEL TESTING FUNCTIONALITY When the PLL_EN pin is LOW, the PLL is bypassed and the FCT88915TT is in low frequency "test mode". In test mode (with FREQ_SEL HIGH), the 2Q output is inverted from the selected SYNC input, and the Q outputs are divideby-2 (negative edge triggered) of the SYNC input, and the Q/2 output is divideby-4 (negative edge triggered). With FREQ_SEL LOW the 2Q output is divideby-2 of the SYNC, the Q outputs divide-by-4, and the Q/2 output divide-by-8.
These relationships can be seen in the block diagram. A recommended test configuration would be to use SYNC0 or SYNC1 as the test clock input, and tie PLL_EN and REF_SEL together and connect them to the test select logic. This functionality is needed since most board-level testers run at 1 MHz or below, and the FCT88915TT cannot lock onto that low of an input frequency. In the test mode described above, any test frequency test can be used.
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IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC
V IN Pulse Generator D.U.T.
VOUT
50pF RT CL 500
Test Circuits For All Outputs
SYNC IN PUT (SYNC (1) or SYNC (0))
1.5V tCYCLE tPD 1.5V
SYN C IN PU T
FEED BACK INPUT
1.5V Q/2 OUTPUT tSKEWALL tSKEWf tSKEWr tSKEWf tSKEWr
Q0-Q4 OUTPUTS tCYCLE
"Q" OU TP UTS
1.5V
1.5V Q5 OUTPUT 1.5V 2Q OUTPUT
Propagation Delay, Output Skew
(These waveforms represent the configuration shown in Figure 4a)
NOTES: 1. The FCT88915TT aligns rising edges of the FEEDBACK input and SYNC input. Therefore, the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as deviation around a center point. 3. If a Q output is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q output would run at twice the SYNC frequency, and the Q/2 output would run at half the SYNC frequency.
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IDT74FCT88915TT LOW SKEW PLL-BASED CMOS CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
FCT XXXX IDT XX Temp. Range Device Type X Speed X Package
J PY 55 70 100 133 88915TT 74
PLCC SSOP 55MHz Max. frequency 70MHz Max. frequency 100MHz Max. frequency 133MHz Max. frequency Low Skew PLL-Based CMOS Clock Driver 0C to +70C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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